The present invention generally concerns xe2x80x9cparallel platexe2x80x9d or xe2x80x9csingle layerxe2x80x9d capacitors as are typically made by metallizing two faces of a thin sheet of ceramic so as to make a ceramic capacitor.
The present invention further concerns high-capacity ceramic capacitors having (i) internal conductive planes connected by (ii) multiple redundant (preferably radiation patterned) vias to (iii) improved, alignment-insensitive and anti-wicking, surface pads to which electrical connection may be made.
Description of the Prior Art
State of the Art in Capacitor Technology Circa 1997, and Industry Impetus for Certain Improvements of All Types
As reported by free-lance writer Hailey Lynn McKeefry in the article xe2x80x9cCapacitor Technology Marches Aheadxe2x80x9d appearing in the February, 1994, issue of Electronic Buyer""s News, capacitors were then, and are now, a mature component in a mature market. Nonetheless to this maturity, U.S. manufacturers are striving mightily to improve both tantalum and ceramic capacitors. xe2x80x9cThe fact that everything you buy performs better and costs less then what you bought last year is what keeps this industry going,xe2x80x9d said Terry Weaver, president and chief operating office at Kemet Electronics Corp., Greenville, S.C. In this sentiment the inventors of the present invention concur.
As with just about any electronic component, the motto of capacitor purchasers and manufacturers alike is xe2x80x9csmaller is better.xe2x80x9d Capacitor manufacturers are working toward cases with smaller footprints and lower profiles. For example, the Sprague division of Vishay Electronic Components of North America and Asia developed a molded surface-mount tantalum capacitor with a rating of 6.8 microfarads in an R-size case. In September, 1997, Myrtle Beach, S.C.-based AVX Corp. announced a low-profile V-size case for its tantalum surface-mount capacitors. The PCS-V series is designed to provide capacitance/voltage (C/V) ratings higher than 3,500 and improved power dissipation. The V case measures less than 7 mmxc3x976 mm, with a height of just 3.45 mm.
In the marketplace for ceramic capacitors (to which the present invention pertains), the 0805 case size remains popular although there is a significant move to 0603s, and even increased interest in 0402s. xe2x80x9cDesigners are leap-frogging the 0805 packages in favor of the 0603s in some designs,xe2x80x9d said Kevin Rafferty, marketing manager for ceramic capacitors at Philips Electronic Components, Jupiter, Fla. Rafferty predicts that 0805sxe2x80x94with a 30% share of ceramic volumexe2x80x94will continue to take the biggest share of the market, while 0603s will claim 20% and 0402s 5%. The remaining 35% will be divided among products in 1206 and larger packages. In 1996, 0603 packages accounted for only 5% of the market share. xe2x80x9cThe 0805s are stable, while 1206 packages are losing share,xe2x80x9d he said.
Part of what is holding the 0402s back is their diminutive size. xe2x80x9cThey are just too hard to handle,xe2x80x9d Kemet""s Weaver said. xe2x80x9cA number of our customers can""t place them at all.xe2x80x9d To combat these complaints, some companies such as Murata Electronics North America Inc. are developing ways of handling the components. The manufacturer has created a small plastic case with a flip top that can hold 50,000 to 80,000 pieces. This box is slipped into a slot on the placement equipment. In comparison, a typical tape-and-reel holds about 5,000 parts. Although Murata developed the bulk cassette technology, others now offer it. For example, Kemet will ship the 0603 and 0402 sizes of its capacitors that use the X7R and C0G dielectrics in cassettes that can hold 15,000 units of the 0603 chips and 50,000 units of the 0402 chips.
Another emerging solution is the use of capacitor arrays, in which several components are encased in a single package. The present invention will be seen to well support capacitor arrays. With these arrays, OEMs are able to avoid the placement issues surrounding very small chips. In addition, they save on-board real estate and component placement costs. A standard array contains two to four chips. However, use of these packages is still limited to specialized niche markets. One of the biggest drawbacks of this packaging strategy is that all of the capacitors in the array have heretofore been required to be of the same value. The present invention will be seen to readily overcome this limitation.
The fact that the Electronic Industries Associate has not settled on a standard case size has also inhibited sales of arrayed capacitors. Heretofore the case size was strongly, even inflexibly, linked to the capacitance value. Therefore standardization of the case sizes was, to some extend, a standardization of the capacitance values with which, for a particular packaging technology, circuit designers could work. The present invention will be seen to sever this relationship, and present a greater opportunity than heretofore of producing a ceramic capacitor of any desired value (within limits) inside a standard case, or a reduced number of standard cases.
A similar trend is occurring in the tantalum capacitor market. xe2x80x9cWe are seeing uses of each case size (A, B, C, and D) going to the next-smallest case size to save real estate, while getting the same values,xe2x80x9d said Willing S. King, marketing manager for tantalum products at AVX. xe2x80x9cIn turn, we are using less material and passing that savings on to the customer.xe2x80x9d There is about a 10% price difference between case sizes, he estimated.
Computer makers primarily use C and D case sizes, while telecommunications and cellular manufacturers, the two biggest markets for tantalum capacitors, prefer the A and B sizes. A standard A case measures about 1.6 mm, while a B case is 2 mm high. Despite some similarities, the ceramic- and tantalum-capacitor businesses are, in fact, very different. In the ceramic marketplace, some of the primary focuses include advancing dielectric technologies and the advent of low-inductance products. Tantalum manufacturers, on the other hand, are concentrating on lowering equivalent-series-resistance (ESR) ratings and increasing C/V ratings.
Two popular dielectrics are the Y5V and X7R. Y5V is a general-purpose dielectric without the tighter tolerances offered by the X7R. It offers an operating temperature range of (approximately) xe2x88x9230xc2x0 C. to +85xc2x0 C., and is favored in cost-sensitive consumer applications. The X7R, which is more temperature stable, can handle from 55xc2x0 C. to +125xc2x0 C. However, the dielectric coefficient K of the Y5V dielectric is approximately 15,000; the K of the X7R dielectric only about 4000. Accordingly, the advantage that a high-dielectric-constant dielectric offers for realizing much higher capacitance in a single chip comes at the expense of temperature stability. There has therefore heretofore been a trade-off: improved dielectric performance with resultantly increased capacitance (for the same form factor) versus enhanced temperature sensitivity. The present invention will again be seen to substantially obviate this concern, and to permit the production of ceramic capacitors of desirably high capacitance by use of only the dielectrics having lower dielectric coefficients.
OEMs have begun to replace tantalum chips with ceramic parts in some instances. xe2x80x9cHigher capacitance values and cost effectiveness made surface-mount ceramic capacitors an increasingly popular alternative to tantalum caps,xe2x80x9d said Philips"" Rafferty. xe2x80x9cOther advantages of ceramic chips include higher breakdown voltages, lower ESR, higher insulation resistance, and better pulse response for frequencies greater than 100 kHz. This means that the capacitance values can be 50% less than the equivalent tantalum caps.xe2x80x9d
Low inductance is also in demand for the PC market, particularly as faster and faster microprocessors are designed into PCs. xe2x80x9cThere has been lots of interest in low-inductance products since the speed of processors is increasing and voltages for processors are dropping to 2.2Vxe2x80x9d Vishay""s Gormally said. xe2x80x9cUsing higher-inductance parts can wreak havoc with those circuits.xe2x80x9d Vitramon has recently introduced a ceramic chip capacitor in the 0612 format with only one-third the inductance (0.3 nanohenry) of its standard counterpart.
Lowered Equivalent Series Resistance, or ESR, is also desired. Tantalum capacitors in a C-case size are available in the range from 4V to 50V with a maximum ESR at 25xc2x0 C. of 250 milliohms to 1,600 milliohms. However, OEMs continue to push for even lower values. State of the art is around 80 milliohms to 100 milliohms. The present invention will be seen to support very low resistance electrical connection to the plates of a ceramic capacitor, thus delivering a desirably low ESR.
State of the Art in Ceramic Capacitor Technology Circa 1997.
As demand for smaller, thinner, and lighter portable equipment, liquid crystal modules, and power supply modules grows, smaller and thinner ceramic capacitors are in greater demand. Since newer equipments tend to require (and provide) both higher performance and longer service life, the demand for ceramic capacitors, as opposed to tantalum or aluminum electrolytic capacitors, is greatly increasing.
To meet the demand, the industry is working, circa 1997, on increasing the capacitance, reducing the size, and improving the dielectric strength of ceramic capacitors. To manufacture a capacitor with a ceramic capacitance of 100 micro F, high technology is required to create a thin-layer dielectric substance of 5xc3x9710xe2x88x926 meters or less, and to, in the case of multiple electrode ceramic capacitors, form capacitors of 300 or more buried layers. To do so, progress has been made in fine-graining ceramic material, particularly composite perovskite type ceramic, so that it can be thin-layered.
Recently achieved increases in capacitance have resulted in, for example, the commercialization by Murata Manufacturing Co., Ltd. (Japan) of its GRM 200 line of ceramic capacitors having up to 22 microfarads capacitance, with contemplated development of ceramic capacitors of up to 100 microfarads capacitance.
Applications of these improved, larger capacitance, ceramic capacitors include power supply modules, liquid crystal modules, and various portable equipments.
The new Murata Manufacturing Co., Ltd. GRM 200 series of large-capacitance monolithic chip ceramic capacitors include: capacitance 10 microfarads/10V of size: 3.2xc3x972.5xc3x971.5 mm; capacitance 22 microfarads/10V of size: 3.2xc3x972.5xc3x972.0 mm; and capacitance 10 microfarads/25V.
When small size is emphasized the sizes may be as small as 2.0xc3x971.25xc3x971.25 mm for the capacitance of 10 microfarads. When increased capacitance is emphasized 47 microfarads may be realized in a 3.2xc3x972.5xc3x971.5 mm size, 100 microfarad in a 4.5xc3x973.2xc3x972.5 mm size. Production of these new capacitors has reportedly been achieved by use of a thin-layer/multi-layer forming technology using improved materials.
Currently, demand for even smaller liquid crystal modules, power supply modules, and portable equipment is greatly increasing. Demand for these new capacitors is expected to expand with the need to downsize this type of equipment. Currently, the new capacitors are used mainly for smoothing in the DC-DC converters of portable equipments, noise-filtering in liquid crystal bias circuits, and smoothing/decoupling in IC power supply lines of various equipments. The capacitors are being produced at levels from 20 to 50 million units per month as of 1996/97.
General Construction and Theory of Single-Layer Parallel-Plate Ceramic Capacitors
Existing xe2x80x9cparallel platexe2x80x9d or xe2x80x9csingle layerxe2x80x9d xe2x80x9cchipxe2x80x9d capacitors are built with two parallel conductive plates separated by a single, insulating dielectric layer that is typically made of ceramic. These single-layer parallel-plate ceramic capacitors have a very useful form factor which renders them suitable for automated assembly into microwave frequency circuits and similar applications. The normal form factor is a rectilinear parallelcpiped body. Dimensions of the chip capacitors can be matched to the width of the strip lines upon which the capacitors are mounted and to which the capacitors electrically connect.
In assembly the bottom face of the chip capacitor is typically soldered or conductive epoxy attached to a conductive surface, or pad. The top face is typically ribbon, or wire, bonded to another connection point.
Most current chip capacitors are made by metallizing two faces of a thin sheet of sintered ceramic typically having a thickness in the rang of 4 mils (inches) to 10 mils (inches). The metallized sheet is then cut into small rectangular bodies by sawing or by abrasive cutting techniques. The sizes of the cut bodies range from, typically, 10 mils (inches) square to 50 mils (inches) square, although some applications use rectangular forms.
While the form factor of these devices is desirable, the amount of capacitance that can be achieved and quality factor of the devices has frequently limited their usefulness. The simplified equation for the capacitance of two parallel plates is C=kA/d; where C is capacitance in farads, k is the dielectric constant of the insulating material between the plates, A is the area of each of opposed plates in square meters, and d is the distance between the plates. Solution of this equation shows that a 20 mil square part (A) having a 5 mils thickness (d) in material having a relative dielectric constant of 100 gives a capacitance of 8 picofarads.
Adhesive Mounting of Single-Layer Parallel-Plate Ceramic Capacitors
Conductive adhesive, and particularly conductive epoxy adhesive, may be used to strongly permanently bond single-layer parallel-plate ceramic capacitors to a substrate. The capacitors are simultaneously (i) adhesively attached, and (ii) electrically connected, to a substrate circuit by first being placed in a puddle of liquid conductive epoxy, which epoxy is then cured. It is intended that the conductive epoxy contact only the underside conductive surface of the capacitor; electrical connection to the topside conductive surface being made by ribbon, or wire, bonding.
Sometimes, however, the liquid epoxy will wick up the sides of the capacitor, especially if these sides are (i) other than exactly perpendicular to the substrate, and/or (ii) too much epoxy is used. The conductive epoxy wicked up the sides of a single-layer parallel-plate ceramic capacitors may flow over onto, and electrically contact, the conductive topside surface of the capacitor, resulting in reduced resistance or even a total shorting of the capacitor.
Some manufacturers have previously gone to extraordinary lengths to angle the edges of their capacitors in order to avoid this problem. Generally, however, features that extend the body of the capacitor, and that thereby serve to isolate one or both of the conductive areas (plates) of its underside and topside surfaces, only serve to reduce the area of the plates for a given physical size, and thus adversely reduce the capacitance of a capacitor of any given size.
Creation of Vias in Ceramic Capacitors and Other Ceramic Electrical Components
The present invention will be seen to concern improvements in the creation of vias, or through holesxe2x80x94through which vias electrical connection can be made by the deposition of metalxe2x80x94in the ceramic electrical components having ceramic-covered or ceramic-encapsulated electrically connectable parts. The improvements are applicable to ceramic capacitors containing electrically conductive plates, but are not limited to ceramic capacitors, being also useful in fabrication of piezoelectric sensors and actuators, for example.
The conventional means for making vias is discussed in U.S. Pat. No. 4,864,465 for a VIAD CHIP CAPACITOR AND METHOD FOR MAKING SAME to William L. Robbins. The Robbins patent concerns a two pole viad chip capacitor activatable from either of its sides. The capacitor has (i) a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; (ii) a first conductor in each of the first vias; (iii) a second conductor in each of the second vias; (iv) a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; (v) and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.
The Robbins capacitor is a conventional-type ceramic chip capacitor solderable at both ends for use on printed circuit boards. The ceramic conventional volume and external form of the ceramic chip capacitor of the present invention will be seen, however, to be of a different nature. Namely, the (nominal) xe2x80x9ctopxe2x80x9d and xe2x80x9cbottomxe2x80x9d of the capacitor have extensive conductive planes, or pads. This permits the new capacitor of the present invention to be machine located and soldered (typically) immediately adjacent integrated circuits in small packages -substantially unlike the Robbins capacitor.
The vias of the Robbins capacitor, and of other ceramic capacitors, may be mechanically punched in the green ceramic sheets, or may be punched through the ceramic sheets by hydraulic jets, before sintering of the multi-layer ceramic capacitor. The punching technique, in particular, continues to work well for the creation of vias in the ceramic capacitors of the present invention and is, indeed, used at a much higher density than heretofore in order to create a greatly increased number of vias per unit area, and overall, than heretofore.
However, fabrication of the improved capacitors of the present invention will also be seen to usefully employ a method of creating vias, or through-holes, in the ceramic of electrical components having ceramic-covered or ceramic-encapsulated electrically connectable parts by use of one or more photosensitive ceramic binders. A number of issued United States patents concern ceramic compositions having photosensitive binders, an exemplary five of which are patents assigned to E.I. Du Pont de Nemours and Company (Wilmington, Del.).
U.S. Pat. No. 4,613,560 to Dueber et al. for a PHOTOSENSITIVE CERAMIC COATING COMPOSITION assigned to E.I. Du Pont de Nemours and Company (Wilmington, Del.) concerns a photosensitive ceramic coating composition which is fired in a substantially non-oxidizing atmosphere comprising an admixture of: (a) finely divided particles of ceramic solids having a particularly defined surface area-to-weight ratio and particle size, and (b) finely divided particles of an inorganic binder having a particularly defined surface area-to-weight ratio and particle size, dispersed in an organic medium comprising (c) an organic polymeric binder and (d) a photoinitiation system, dissolved in (e) photohardenable monomer and (f) a volatile organic solvent.
U.S. Pat. No. 4,912,019 to Nebe et al. for a PHOTOSENSITIVE AQUEOUS DEVELOPABLE CERAMIC COATING COMPOSITION assigned to E.I. Du Pont de Nemours and Company (Wilmington, Del.) concerns a photosensitive ceramic coating composition which is fired in a substantially non-oxidizing atmosphere comprising an admixture of: (a) finely divided particles of ceramic solids having a surface area-to-weight ratio of no more than 10 m2/g and at least 80 wt. % of the particles having a size of 1-10 xcexcm, and (b) finely divided particles of an inorganic binder having a glass transition temperature in the range from of 550xc2x0 C. to 825xc2x0 C., a surface area-to-weight ratio of no more than 10 m2/g and at least 90 wt. % of the particles having a size of 1-10 xcexcm, the weight ratio of (b) to (a) being in a range from 0.6 to 2, dispersed in an organic medium comprising (c) an organic polymeric binder, and (d) a photoinitiation system, dissolved in (e) photohardenable monomer, and (f) an organic medium. An improvement to this composition comprises an organic polymeric binder containing a copolymer or interpolymer of a C1-C10 alkyl acrylate, C1-C10 methacrylate, styrene, substituted styrene or combinations thereof and an ethylenically unsaturated carboxylic acid, wherein a moiety in the binder derived from the unsaturated carboxylic acid comprises at least 15 wt. % of the polymer and wherein the binder has a molecular weight not greater than 50,000 and wherein the composition upon imagewise exposure to actinic radiation is developable in an aqueous solution containing 1% by weight sodium carbonate.
Similarly, U.S. Pat. No. 4,959,295 is for a PROCESS OF MAKING A PHOTOSENSITIVE SEMI-AQUEOUS DEVELOPABLE CERAMIC COATING COMPOSITION; U.S. Pat. No. 4,925,771 is for a PROCESS OF MAKING PHOTOSENSITIVE AQUEOUS DEVELOPABLE CERAMIC COATING COMPOSITION INCLUDING FREEZE DRYING THE CERAMIC SOLID PARTICLES; and U.S. Pat. No. 4,908,296 is for PHOTOSENSITIVE SEMIAQUEOUS DEVELOPABLE CERAMIC COATING COMPOSITION.
The present invention contemplates a ceramic capacitor of conventional volume and external formxe2x80x94meaning a parallelepiped body having exterior pads to which electrical connection is madexe2x80x94that is enhanced in its capacitance by dint of including at least one interior metallization plane, and preferably one or more pairs of interior metallization planes, that are parallel to capacitor surfaces where exist pads and/or traces. Electrical connection between these interior metallization planes and the surface pads and/or traces (which pads and traces need not be, and which commonly are not, coextensive with the planes) is made though (i) abundant (ii) redundant vias.
In accordance with the physical law that capacitance between two conducting planes is inversely proportional to the distance of separation, the capacitance between these interior metallization planesxe2x80x94which capacitance is seen at the exterior of the capacitor when these internal planes are electrically connected to the exterior pads xe2x80x94is greater than that capacitance which would alternatively be seen between opposed exterior pads (which have heretofore served as the electrodes) should no electrically connected interior metallization plane(s) be present.
The present invention further contemplates that each interior metallization plane within a ceramic capacitor so constructed should be redundantly, and preferably massively redundantly, electrically connected to associated exterior pads by plural, and more preferably by multiple, vias. By this construction the enhanced-capacitance ceramic capacitor may be reliably conventionally fabricated in huge arrays (typically many thousands of capacitors) on workpiece xe2x80x9cbarsxe2x80x9d regardless than any single one via, and some few vias, may not be properly located. Additionally, the redundant vias make a low-resistance electrical connection useful at high frequencies.
Moreover, the many vias are preferably located in a dense uniform pattern; normally a regular pin grid array. Because both (i) the interior metallization planes internal to the capacitor, and the (ii) exterior metallizations in the forms of traces and pads, do not commonly occupy all the area of the capacitor, this makes that many vias xe2x80x9clead to nowhere,xe2x80x9d connecting to metallization at only one end (a xe2x80x9cmissed viaxe2x80x9d) or at neither end (an xe2x80x9cempty viaxe2x80x9d). These xe2x80x9cmissedxe2x80x9d and/or xe2x80x9cemptyxe2x80x9d vias are intentional: they permit fabrication of diverse capacitors (i) by uniform processes in which (ii) alignment is not critical. In the course of capacitor fabrication, those vias that actually connect to metallization (which is typically more than 50%, but less than 100% of all vias) fill with metal. Those vias that do not serve to connect to metallization areas tend to close off, and heal, during annealing of the capacitor ceramic. The small regions where these xe2x80x9cvestigial,xe2x80x9d xe2x80x9cemptyxe2x80x9d vias are present do not significantly affect capacitor performance.
The present invention further contemplates a ceramic capacitor having amply numerous, and amply large exterior pads so as to easily readily support positionally tolerant electrical connection. In particular, the exterior pads, of which there may commonly be but two located on opposed sides of the ceramic capacitor, are much, much larger than are the egress areas of (preferably multiple) vias that connect to interior metallization planes that are within the capacitor. The exterior pads are, indeed, so large as to span between multiple vias. Equivalently, it may be said that multiple vias connect each interior metallization plane to an associated external surface pad, and that the vias are thus xe2x80x9credundant.xe2x80x9d
The present invention still further contemplates that all the collective large-area exterior pads (or pad) on at least one, and preferably both, surfaces of the capacitor should be withdrawn from the edges of the capacitor. It is thereby beneficially promoted that (insulating) epoxy adhesive will not wick onto the conductive pads of the capacitor, potentially interfering with electrical connection to these pads, during adhesive surface mounting of the capacitor.
Still other niceties are present in the improved capacitors, particularly including (i) parallelepiped ceramic bodies that are (by dint of the close interior metallization planes) of sufficient size and thickness so as to substantially avoid fracture during routine handling (regardless that the capacitance is much higher than even that which would normally be realized from a ceramic capacitor so excessively thin so as to typically be undesirably fragile), and (ii) rounded edges.
Finally, the present invention contemplates improved methods of realizing the abundant multiple vias; namely, the vias are either (i) stamped as a grid array in the green ceramic sheets (from which the ceramic capacitor is made), or else (ii) patterned with radiation, normally ultraviolet light, in a ceramic dielectric tape having a photosensitive binder. In the case of method (ii), unexposed areas of the tape are cost effectively washed out with solvent, instead of being punched out, before sintering of the ceramic so as to easily and accurately create multitudinous holes.
Howsoever abundantly perforated, the perforated ceramic tape is used to make wafers of arrayed ceramic capacitors the future vias are accurately precisely positionally located. Notably the ample, and amply large pads, that are, as previously explained, positionally tolerant of later external electrical connection are to some extent made possible by the precise location of the many vias. Namely, the vias typically serve to define the boundaries of the pads, and the precise location of these vias permits the pads, even as they are preferably withdrawn from the edges of the capacitor, to advantageously occupy all available surface area, and to partition this area optimally.
Quite simply, the interior structures and geometries of the ceramic capacitor (the potentially many metallization planes, and the many permissible geometries of these metallization planes) are divorced from the exterior structures and geometries of the same ceramic capacitor (the potentially many pads and vias, and the many permissible geometries of these pads and vias), and vice-versa. Each region is substantially optimized for its function without making such compromises to the function of the other region as have heretofore been made. For devices that are made in quantities of hundreds of millions of units, these improvements are worth making.
Accordingly, the present invention offers the following advantages.
The usefulness and/or capacitance of ceramic capacitors of conventional external shapes and forms is extended either by (i) producing a higher capacitance for a given dielectric formulation, (ii) producing the same capacitance with a dielectric formulation that is either less expensive and/or less temperature sensitive, and/or (iii) producing the same capacitance with the same dielectric formulation in a geometrically smaller volume.
A conventional single-layer ceramic capacitor has a thickness of 5 mils or greater whereas the thickness of the active layer of the capacitors of the present invention is typically only 0.5 mils or less. This accords a ten times (xc3x9710) improvement in capacitance.
This improvement in capacitance can be xe2x80x9ctraded offxe2x80x9d to produce a capacitor of equal size with improved temperature stability. For example, a conventional 5 volt ceramic capacitor with an 85xc2x0 C. maximum temperature rating could be replaced with the X7R dielectric material, according a maximum temperature rating of 125xc2x0 C., while maintaining equal capacitance by use of the present invention.
Meanwhile, user yields are improved. Namely, the area(s) and/or the location(s) of surface pads and/or traces are optimizedxe2x80x94especially as such may be withdrawn slightly from the edges of the capacitor to alleviate shorts during adhesive mountingxe2x80x94so as to improve user yields in mounting and connecting the capacitors without sacrificing either (i) capacitance nor (ii) small size.
Meanwhile, ESR is excellent. The preferred abundant, and redundant, vias connecting the ample, reliably connected surface pads to the internal metallization planes ensure a low Equivalent Series Resistance (ESR), and thus good high-frequency performance.
Meanwhile, reliability is high. The new capacitors are a true monolithic structure, with the potentially delicate electrodes buried within the three-dimensional body of the capacitor while the surface pads and traces are typically made robust, and resistant to all temperatures and atmospheres to which the capacitor may be exposed. The surface material is, in particular, unlikely to delaminate, nor to corrode.
The capacitors of the present invention are truly monolithic devices, being co-fired in all layers at the same time. It is known in the ceramic business that the atmospheric sintered surface of a ceramic piece is different than the interior of the ceramic. In particular, the oxidation potential is different at the surface than in the interior. The surface typically comes into contact with a dissimilar ceramic during processing. Zirconia oxide carriers such as those supplied by Applied Ceramic of Georgia are commonly used as sintering aids. Considerable pre-processing or xe2x80x9cseatingxe2x80x9d of the ceramic bodies is often done to reduce the diffusion of these zirconia sintering aids into the capacitor and into the capacitor dielectric compounds during high temperature processing.
In the traditional, single-layer ceramic capacitors, the metallized surface conduction areas typically use glass frits as the adhesion mechanism to adhere the metal to the ceramic. The resulting system typically has a glass-rich zone at the ceramic surface.
Both the (i) zirconia and the (ii) glass are adverse to the creation of uniform, quality capacitor electrodes. (Where the (i) zirconia and/or the (ii) glass is present, there the metal is not.) By putting the capacitance forming elements into the interior of the ceramic capacitor, the present invention completely avoids the issue of surface anomalies.
The present invention mandates vias. Thus it is somewhat disingenuous to claim that vias are an advantage of the invention. It might better be said that the concept of abundant redundant vias is, as expressed for capacitors in the preferred embodiment of the present invention, applicable to other devices, including piezoelectric sensors. The redundant via holes all but eliminate the requirement for precise alignment between layers in the built-up ceramic capacitor. Because connection is assured by some of the redundant vias regardless of mis-alignments(s) and/or misregistration(s) of layers, manufacturing efficiency is enhanced. The optimum via hole size, and spacing, can even be chosen mathematically and geometrically to, given the location(s) and size(s) of each internal metallization plane(s), best and most reliably connect this plane (these planes) to one or more surface pads and/or traces. Usually this xe2x80x9cbest and most reliablexe2x80x9d optimization is trivial; the preferred vias are preferably 2 mils in diameter on 10 mil centers in square xe2x80x9cpin gridxe2x80x9d arrays over the entire planar area of the ceramic capacitor, howsoever large. In other words, a regular grid array of some hundred or thousands of vias is typically punched, hydraulically drilled, laser drilled, or photochemically patterned and removed in selected ceramic layers of even the smallest capacitors. These small vias at this small spacing makes that at least 4-5 vias are redundant for even the smallest interior or surface connection areas (i.e., planes or pad) as of yet employed.
In summary, the new and improved ceramic capacitor has enhanced capacitance. It electrically connects reliably and well, with but small Equivalent Series Resistance (ESR). It adhesively connects reliably without causing undesired interference with the electrical connection. It is rugged, and resists breakage or chipping during normal handling, including by machine. It may be sophisticated, containing several smaller capacitors, which may be of differing values, in a single, monolithic package. Nonetheless to a sophisticated internal structure, the surface pads and/or traces to which electrical connection(s) is (are) made may be amply sized and well situated. The new capacitor is, of course, completely compatible with existing machines, circuits and processes.
These and other aspects and attributes of the present invention will become increasingly clear upon reference to the following drawings and accompanying specification.
In accordance with one of its aspects, the present invention may be considered to be embodied in a capacitor having a ceramic body (of a finite thickness) and at least one area of metallization to which electrical connects may be made on a portion of each of two opposite exterior substantially co-planar surfaces of the ceramic body. In other words there are at least two, and most commonly exactly two, opposed metallization areas, or pads, or simply xe2x80x9cexterior metallizations.xe2x80x9d (So far, this is the most common form of ceramic capacitor in the world.)
At least one, and most typically two, metallization planes are both interior to the body and substantially co-planar to the exterior metallizations. Each of these planes is thus more closely situated to each exterior metallization than the exterior metallizations are to each other.
At least one via, and most commonly a great number of vias, electrically connects, and most commonly redundantly electrically connects, each one of the (typically two) exterior metallizations to an associated (i.e., closest) interior metallization plane. This connection is to the end that, because capacitance between two conducting planes is by physical law inversely proportional to the distance of separation, the capacitance between at least one pair of exterior metallizations on opposite surfaces will be greater than that capacitance which would alternatively exist should no electrically connected interior metallization plane be present.
The collective area or areas of the exterior metallization upon at least one surface, and preferably both opposed surfaces, of the ceramic body is preferably not substantially co-extensive with, and is less than, the entire surface area of a face of the ceramic capacitor. Instead, this collective area is instead preferably somewhat smaller than is the surface area of the face, and is in particular withdrawn from the edges of the face. By this construction the associate interior metallization plane(s) is (are) larger than are the collective exterior metallization areas. More importantly, the reduced-area exterior metallizations are slightly withdrawn from the edges and sides of the ceramic body. By this construction the undesirable wicking of insulating adhesives, normally epoxy adhesive, onto the metallization areas (thus undesirably interfering with electrical connection) is avoided during adhesive surface mounting of the capacitors.
As previously explained, the finite thickness of the ceramic body is normally sufficient so as to permit routine handling of the ceramic capacitor without breakage. This increased thickness is now without penalty to the capacitance.
Furthermore, at least one edge of one surface, and preferably all edges of all surfaces, are rounded so as to reduce the propensity of these edges to chip. These rounded edges, which heretofore reduced the metallization area and the net capacitance, are again now realized without penalty to the capacitance.
In accordance with another of its aspects, the present invention may be considered to be embodied in a capacitor having a ceramic body (of a finite thickness) and ample large exterior metallization areas, or pads, on each of opposed surfaces to the body (to which pads electrical connections may easily be made).
Notably, a plurality of metallization planesxe2x80x94normally two such metallization planesxe2x80x94are located interior to the body and co-planar to the exterior metallization areas.
A number of vias electrically connect each one of the interior metallization planes each to associated one of the exterior pads. This connection is redundant; each pad is electrically connected to its associated interior metallization plane by multiple vias. Each (connected) pad is much larger than the egress area of any one via. Finally, and in accordance with the physical law that capacitance between two conducting panes is inversely proportional to the distance of separation, the capacitance between at opposed pairs of exterior pads on opposite surfaces is greater than that capacitance which would alternatively exist should no electrically connected interior metallization plane be present.
In total, this construction makes that the ceramic capacitor is simultaneously of (i) enhanced capacitance due to its interior metallization planes while it (ii) supports reliable electrical connection to, ultimately, these interior metallization planes. It does so support this reliable electrical connection both because (i) the vias are redundant, and (ii) the pads are larger than are the egress areas of the vias, and are thus positionally tolerant of electrical connection (to other circuitry exterior to the capacitor).
In accordance with yet another of its aspects, the present invention may be considered to be embodied in a method of manufacturing a ceramic capacitor having vias overlying an electrically conductive structure to which electrical connection may be made though the vias.
The method includes placing upon at least one surface of a parallelepiped ceramic body having a finite thickness a first metallization plane. An electrically insulating ceramic sheet or tape, suitable in a portion thereof to form a layer of a laminate electrical component, having a photosensitive binder is applied over this first metallization plane.
The entire laminate structure of (i) the holed ceramic sheet or tape layer upon (ii) the first metallization plane upon the (iii) parallelepiped ceramic body is then fired so as to create a monolithic sintered body. A second metallization plane is patterned into at least one electrically conductive pad upon the sintered body, and into the holes of the sintered holed ceramic sheet or tape layer, so as to create vias in the holes. Notably, at least two of these vias electrically redundantly connect the first metallization plane to the at least one electrically conductive pad of the second metallization plane.
When considered to be embodied in an electrical component, this aspect of the invention may be recognized to be expressed as an electrically conductive region under a ceramic layer to which region electrical connection is redundantly made to electrically conductive pad regions on the top of the ceramic layer by plural vias for each said pad region, the vias being formed in the overlying ceramic layer which had in its green state a photosensitive binder by patterning this green state ceramic layer with radiation, washing away unexposed ceramic with solvent so as to form patterned holes, and sintering the ceramic and the electrically conductive region and the electrically conductive pad regions so that the holes become filled with metal and become vias.
The present invention further contemplates devices in which two or more green state ceramic layers having vias formed therein are stacked upon each other to create tiers of vias, interconnected by intermediate metallization areas. The present invention also contemplates series capacitors, R-C devices having a capacitor in either series or parallel with a resistor, and devices that are reversibly mountable, all taking advantage of redundant electrical connections by vias between interior and exterior metallization planes.
The present invention further contemplates a method in which the capacitors may be constructed from the bottom up to eliminate the need for flipping the chip to obtain top and bottom metallizations.